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wenbo

03/02/2021, 7:18 PM
Hi @User, I am also trying netgen with the LVS check but got some issues. The comp.out file shows
Flattening unmatched subcell *
in the beginning, is this an expected behavior? Also, I found the
sky130_fd_sc_hd__conb_1/short
resistors in
sky130_fd_sc_hd.spice
have three ports, while the
sky130_fd_pr__res_generic_po
resistors extracted from magic only have two ports, which is causing an LVS issue in my case. I have attached my files below. My magic version is 8.3.134 and the open_pdk version is 1.0.134. Thanks in advance!