``` drc why MiM2 cap spacing to via3 lt 0 08um cap2m 8 via3 open-source-silicon.dev #analog-design

```% drc why MiM2 cap spacing to via3 < 0.08um ...

Weston Braun

05/23/2021, 4:33 AM

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% drc why
MiM2 cap spacing to via3 < 0.08um (cap2m.8 - via3.4)

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