https://open-source-silicon.dev logo
#analog-design
Title
# analog-design
j

Jorge Marin

12/31/2021, 12:56 PM
Hello all, I have the following issue: I'm doing LVS of the topcell and I'm getting net mismatch in one of the cells. This cell had some issues for LVS since it was generating wrappers for mosfet devices for the magic layout netlist in which the bulk terminal appeared inside the wrapper but not as a wrapper pin, and thus it was counting extra nets for each bulk nodes inside each device that had a wrapper. To solve this i extracted using "ext2spice lvs; ext2spice hierarchy off; ext2spice", and since the block has only mosfets this is not an issue and the LVS after this succeeds. When integrating the cell into the top, I can't do the "ext2spice hierarchy off" trick since it netlists only the high level blocks of the top level. And when doing the "hierarchy on" alternative, it generates the extra bulk nets mentioned above and fails for net mitmatch. Any advice on how to solve this? I'm quite sure the connections are OK, it's only matter of how the netlists are generated.