[Last 3 hours] - Analog Bandgap IP design using 130nm PDK - Content Gentle reminder - Workshop registration closes in 3hrs. Best and economical way to enter Analog design profiles Day 1 – BGR Theory and Lab setup • Why temperature-independent voltage/current references for ICs • Realization of BGR voltage reference. • Circuit realization of a self-biased BGR and introduction to PTAT/CTAT current source Day 2 – BGR Labs and post-layout simulations • BGR components circuit simulations • Steps to combine BGR sub-circuits and BGR full design simulation • Post Layout simulations • Steps to combine layouts Registration link - https://www.vlsisystemdesign.com/bandgap-ip-design-using-sky130-technology-node/