Hello I'm stuck while designing a SAR ADC. My buil...
# analog-design
Hello I'm stuck while designing a SAR ADC. My building blocks (DAC, comparator, bootrstrap switch) seem to work seperatly, but when I try to connect them some errors happen which I can't explain for myself. For example; I have a 9 bit -merged cap DAC, which works fine seperatly. If I copy paste it and rename the nodes, everything is still ok. But then when I change the bit input for the MSB cap from 1.8, to 0 xscheme fails. How my schematic works; I have two capacitve DAC arrays, with each capacitor connected to some switches to change between Vdd, Vdd/2 and Vgnd. I first sample the input of the top plates by the bootstrap switch, and afterwards I switch the caps from LSB to MSB all to vdd if Bx =0 . Now when I change this Bx for the MSB cap to 1.8, it should be switched to 0, but this results in the error below. I will attach schematic, output, spice and raw file for the working and not working case of the example. Please ask away if I didn't explain it clear. And let me know if anybody has some idea's what I can test or what is wrong. Kind regards Faedra