@User (@User): The change I just committed to netgen (on the opencircuitdesign.com repo) should solve the problem with the large number of symmetric partitions with a few elements each. The picoRV32 example now runs on my machine in two minutes. It seems that now I have to have a black-box representation of the conb module in the synthesis netlist to make the netlists match because the synthesis netlist shows only the LO pin in those cells---but this is something I thought I had fixed recently. Also I thought these netlists were matching earlier today without that addition. I am investigating that one, now.