@User/ @User: I just pushed to the opencircuitdesign.com netgen repository a fix to netgen to deal with verilog netlists where cells are missing pins that don't connect to anything; this shows up a lot with the "conb" cells where, say, only the LO output is used; the verilog netlist typically will not show the HI pin at all, leaving netgen to toss in a placeholder pin to represent it. That was not being done correctly before, causing netlist mismatches unless a black-box entry was used for the "conb" cell (this problem shows up in Andrew's picoRV32 example). I think this commit solves all the outstanding issues in netgen that I know about.