#40 Latches not mapped by yosys to skywater-130 cells Issue opened by growly Running the OpenLane flow on the trivial latch

module test_latch (
  input wr_en,
  input a,
  output b
);
​
  reg a_latch;
​
  always @(*) begin
    if (wr_en)
      a_latch = a;
  end
​
  assign b = a_latch;
endmodule

fails synthesis. Yosys correctly infers a

$_DLATCH_P_

primitive but cannot map this to a suitable cell, like Skywater 130's

dlxtp

cell. Cadence Genus will do this:

module test_latch(a, wr_en, b);
  input a, wr_en;
  output b;
  wire a, wr_en;
  wire b;
  wire n_0, n_2;
  sky130_fd_sc_hd__inv_8 g4(.A (n_0), .Y (b));
  sky130_fd_sc_hd__inv_1 g5(.A (n_2), .Y (n_0));
  sky130_fd_sc_hd__dlxtp_1 a_latch_reg(.GATE (wr_en), .D (a), .Q (n_2));
endmodule

Yosys seems to need special tech-mapping for this primitive, which is provided by (for example) FPGA targets, but not for Skywater. I created a test mapping /openLANE_flow/dlatchp.v

module \$_DLATCH_P_ (input E, input D, output Q);
  sky130_fd_sc_hd__dlxtp_1 _TECHMAP_REPLACE_ (
    .GATE(e),
    .D(D),
    .Q(Q));
endmodule

and inserted

techmap -map /openLANE_flow/dlatchp.v

into

scripts/synth.tcl

to make sure the mapping was run. This seems to correct the issue and synthesis passes. The flows then continues before segfaulting on the

replace

command. So maybe I did it wrong. efabless/openlane