#67 How to modify config.tcl for simple combinational circuits? In which there in no clock. Issue opened by mdzakirhussain Let's take the following example module fa(a,b,c,sum,co); input a,b,c; output sum,co; assign sum=a^b^c; assign co=a&b|a&c|b&c; endmodule In the above example there is no clock, how do I modify the config.tcl I tried commenting the following it is give error, and by keeping that as well the same issue. Please help. Fill this set ::env(CLOCK_PERIOD) "10" set ::env(CLOCK_PORT) "clk" set ::env(CLOCK_NET) $::env(CLOCK_PORT) efabless/openlane