25 new commits pushed to `staging` `ede7fd88` - Show exit code of failing tools `5d0f462a` - Remove addspacers `018e03db` - Add a --bus-sort option to the I/O placer `dddf7722` - Rewrite canoncial verilog netlist only once `3c28abc6` - Support labelling of core-facing pad pins `6f044524` - Some style fixes and info messages `89318a4f` - Add yet another padframe generator `b34bb8de` - Update TR `f4bb7112` - Fix typo in init_floorplan and set DIE_AREA `ce8d1be0` - SW_MS benchmark update (Oct. 23rd) `f310c172` - separate timing optimizations from placement and move it after CTS `e08882ca` - Revert "separate timing optimizations from placement and move it after CTS" `22f1fa08` - Update padring (support for '.' DEF names) `8db1ed28` - don't segfault if macro is not found `c1c11796` - SW_HD benchmark updated (Oct. 26th) `28514887` - Automatically read IOs verilog as black boxes `4b592685` - Better support for macro placement `d0fad7fe` - label_macro_pins.py can read more than one LEF `b2d606ec` - Place macros within the padframe by default `21ffcdaf` - Exclude tap cells from detailed placement padding `88b1b85e` - Add a design for DFF-based synthesized memory `3095d5e4` - Make default synth_ram smaller `20ae9fd5` - SW_HS benchmark update (Oct. 31st) `8ba6b1c6` - minor doc updates `0bf324ec` - Merge branch 'develop' into staging efabless/openlane