#84 missing connections in generated spice netlist Issue opened by jeras Using rc4. I have synthesized the

inverter

to try running a spice simulation. The generated spice file was

designs/inverter/runs/07-11_21-11/results/magic/inverter.spice

. I expected a full parasitic extraction netlist, but I am actually more happy with what I got, which is a netlist of standard cells (including capacitors filler and tap cells). After I tried to create an example simulation and I got the next error.

Error: too few nodes: xfiller_0_15 vgnd vpwr sky130_fd_sc_hd__decap_12

The affected line in the spice netlist is:

XFILLER_0_15 VGND VPWR sky130_fd_sc_hd__decap_12

The problem seems two missing connections for ports

VNB

&

VPB

for a

decap

cell.

.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
M1000 VPWR VGND VPWR VPB phighvt w=870000u l=4.73e+06u
+  ad=4.524e+11p pd=4.52e+06u as=0p ps=0u
M1001 VGND VPWR VGND VNB nshort w=550000u l=4.73e+06u
+  ad=2.86e+11p pd=3.24e+06u as=0p ps=0u
.ends

The same ports are also present on filler cells and also not connected in the netlist.

.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
.ends

Interestingly, sub-circuit instances are also not named consistently.

XFILLER_*_*

is used for

decap

and

fill

cells, some instances use the

XPHY_*

name. efabless/openlane