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Title
a

Aireen Amir Jalal

11/13/2020, 7:25 AM
Hello @User, @User, I tried to run the DFFRAM RTL on openlane flow. I git cloned @User’s main branch and copied over the verilog files into my working directory as shown in first image. I also drafted a config.tcl file as shown in second image and ran the openlane flow. I got an error in the synthesis stage : `ERROR: Module `\sky130_fd_sc_hd__clkbuf_4' referenced in module `\DFFRAM' in cell
\DOBUF[31]' is not part of the design.
I understand the fact here that the
sky130_fd_sc_hd__clkbuf_4
module is instantiated here so, I tried adding the path to the verilog file containing this module as follows:
glob /home/merlproj/backend-tools/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
, but as this verilog file itself contains multiple `include statements the flow didn't proceed further and gave an error as shown in third image. Can you please guide on how to proceed further. Thanks