#93 Design Always Fails Synthesis after Updating to Develop Issue opened by TsaiAnson I have a design that synthesizes properly on

rc4

but fails when I updated OpenLane to

develop

(nothing else changed). The advice from Slack is to increase the clock period and double check the clock, but those did not resolve the issue. Below are more details: Error:

[ERROR]: during executing: "sta /openLANE_flow/scripts/sta.tcl |& tee >&@stdout /openLANE_flow/designs/mac_cluster/runs/17-11_00-16/logs/synthesis/opensta.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child killed: segmentation violation

[ERROR]: Please check sta  log file
[ERROR]: Dumping to /openLANE_flow/designs/mac_cluster/runs/17-11_00-16/error.log

Config:

# User config
set ::env(DESIGN_NAME) mac_cluster

# Change if needed
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1

# Fill this
set ::env(CLOCK_PERIOD) "200"
set ::env(CLOCK_PORT) "clk"

set ::env(SYNTH_MAX_FANOUT) 7
set ::env(PL_TARGET_DENSITY) 0.35

set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
	source $filename
}

Note: I've also tried changing the parameters a bit to see if anything changes, but the error is consistent. Repo of OpenLane design: https://github.com/TsaiAnson/exampleDesignOpenLaneMACCluster ^ This design synthesizes fine on

rc4

while fails on

develop

. Slack Post (openlane channel): https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1605399551389700 Could someone take a look for the issue? Thanks in advance. efabless/openlane