#95 Parameterised black box fails verilog2def Issue opened by growly We have a design that instantiates a submodule. When converting that module to a hard block, we leave the parameters in:

mac_cluster #(
  .MAC_CONF_WIDTH(MAC_CONF_WIDTH),
  .MAC_MIN_WIDTH(MAC_MIN_WIDTH),
  .MAC_MULT_WIDTH(MAC_MULT_WIDTH),
  .MAC_ACC_WIDTH(MAC_ACC_WIDTH),
  .MAC_INT_WIDTH(MAC_INT_WIDTH)
) macaroni ( /* redacted */ );

Even though the

mac_cluster

module is marked as

(* blackbox *)

, Yosys generates this instantiation in the output verilog:

mac_cluster #(
    .MAC_ACC_WIDTH(32'sb00000000000000000000000000100000),    /* this is the error line */
    .MAC_CONF_WIDTH(32'sb00000000000000000000000000000100),
    .MAC_INT_WIDTH(32'sb00000000000000000000000000101000),
    .MAC_MIN_WIDTH(32'sb00000000000000000000000000001000),
    .MAC_MULT_WIDTH(32'sb00000000000000000000000000010000)
  ) macaroni ( /* redacted */ );

The parameters appear to be a problem for

verilog2def

, which emits this error to its log and then fails to include the module in the output DEF:

Error: /openLANE_flow/designs/250_mac_tile/runs/debug/results/synthesis/mac_tile.synthesis.v, line 165106 syntax error, unexpected '.'.

However, the flow continues, later failing when the macro cannot be found to place.

Placing the following macros:
{'macaroni': ['5000', '5000', 'N']}
Design name: mac_tile
Traceback (most recent call last):
  File "/openLANE_flow/scripts/manual_macro_place.py", line 115, in <module>
    assert not macros, ("Macros not found:", macros)
AssertionError: ('Macros not found:', {'macaroni': ['5000', '5000', 'N']})

• It doesn't make sense to parameterise a hardened macro • It's annoying to have to comment out parameters • A sensible error should be emited when verilog2def fails like this efabless/openlane