#100 ABC/Yosys does not map muxes Issue opened by ryanthornton Similar to #40 and #97, Yosys is not scripted to infer muxes. Changes similar to the linked issues allow Yosys and ABC to infer and map 2 and 4 muxes. In

${OPENLANE_ROOT}/scripts/synth.tcl

, I added the following

# handle technology mapping of 4-MUX, and tell Yosys to infer 4-muxes
if { [info exists ::env(SYNTH_MUX4_MAP)] && [file exists $::env(SYNTH_MUX4_MAP)] } {
  muxcover -mux4 
  techmap -map $::env(SYNTH_MUX4_MAP)
  simplemap
}

# handle technology mapping of 2-MUX
if { [info exists ::env(SYNTH_MUX_MAP)] && [file exists $::env(SYNTH_MUX_MAP)] } {
  techmap -map $::env(SYNTH_MUX_MAP)
  simplemap
}

Create

${PDK_ROOT}/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux_map.v

and

${PDK_ROOT}/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux4_map.v

with the following modules: (replacing the technology mapping as desired) mux_map.v:

module \$_MUX_ (
    output Y,
    input A,
    input B,
    input S
    );
  sky130_fd_sc_hd__mux2_1 _TECHMAP_MUX (
      .X(Y),
      .A0(A),
      .A1(B),
      .S(S)
  );
endmodule

mux4_map.v:

module \$_MUX4_ (
    output Y,
    input A,
    input B,
    input C,
    input D,
    input S,
    input T
    );
  sky130_fd_sc_hd__mux4_1 _TECHMAP_MUX4 (
      .X(Y),
      .A0(A),
      .A1(B),
      .A2(C),
      .A3(D),
      .S0(S),
      .S1(T)
  );

endmodule In

${PDK_ROOT}/$::env(PDK)/libs.tech/openlane/config.tcl

, add

# MUX4 mapping
set ::env(SYNTH_MUX4_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux4_map.v"

# MUX2 mapping
set ::env(SYNTH_MUX_MAP) "$::env(PDK_ROOT)/$::env(PDK)/libs.tech/openlane/$::env(STD_CELL_LIBRARY)/mux_map.v"

Finally, the desired muxes must be removed from all appropriate no_synth.cells files. efabless/openlane