Hello, I have been able to make some progress thanks to the help of a couple folks but I am now facing some issues with yosys. I am seeing the next error when running _make user_project_wrapper_ after instantiating my design (the example works fine):

5. Executing Verilog-2005 frontend: /project/openlane/user_project_wrapper/../../verilog/rtl/custom_core/inc/core_types.vh
/project/openlane/user_project_wrapper/../../verilog/rtl/custom_core/inc/core_types.vh:9: ERROR: syntax error, unexpected TOK_ID, expecting ',' or '=' or ';' or '['
[ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/synthesis/yosys.log |& tee >&@stdout"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
child process exited abnormally
 
[ERROR]: Please check yosys log file
[ERROR]: Dumping to /project/openlane/user_project_wrapper/runs/user_project_wrapper/error.log

As you can see, it reports a syntax error on _core_types.vh_ file but looking at the file it is a simple function:

function automatic is_r_type_instr;
    input logic [`INSTR_OPCODE_RANGE] opcode;
    begin
        is_r_type_instr = 1'b0;
        if ( (opcode == `INSTR_ADD_OPCODE)
            |(opcode == `INSTR_SUB_OPCODE)
            |(opcode == `INSTR_SLL_OPCODE)
            |(opcode == `INSTR_SRL_OPCODE)
            |(opcode == `INSTR_ADDI_OPCODE))
                is_r_type_instr = 1'b1;
    end
endfunction

It is important to note that the feature I am trying to integrate within caravel is functional and has been tested on a different environment. It compiles fine with verilator and I am able to perform simulations, so I am not sure if the issue is on yosys side. Looking at the slack messages I saw that someone had a similar problem and it was related to yosys and some problems supporting System Verilog. I would appreciate if someone can confirm that yosys do not support SV or if I need to add some special define/parameter on the Makefiles to be able to use System Verilog on my design. It is important to note that my design is pretty big and it is entirely done with SV so it is unlikely that I can change all code to verilog in a couple days.