Back to step 1 If I start with a fresh caravel repo at branch develop make user_proj_example make user_project_wrapper Both build without errors. Now if I replace verilog/rtl/user_proj_example.v with my verilog, using a top module name of user_proj_example make user_proj_example Synthesizes correctly However, if instead I replace verilog/rtl/user_project_wrapper.v, using a top module name of user_project_wrapper, I get the folling error. make user_project_wrapper OpenROAD 0.9.0 d03ebfc244 This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. Error: cannot open '/.openroad'. Warning: /home/jcyr/openlane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib, line 31 default_operating_condition tt_025C_1v80 not found. Notice 0: Reading LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged_ unpadded.lef Notice 0: Created 13 technology layers Notice 0: Created 25 technology vias Notice 0: Created 439 library cells Notice 0: Finished LEF file: /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/merged _unpadded.lef Error: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wr apper.synthesis.v, line 4 syntax error, unexpected REG. Error: /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wr apper.synthesis.v, line 5 syntax error, unexpected REG. Any idea what I'm doing wrong?