Argh! Ok replacing openlane_proj_example with my verilog and using exactly the save module declaration for openlane_proj_example, I get:

make user_proj_example

Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/results/placement/user_proj_example.placement.def
[INFO]: Setting output delay to: 2.0
[INFO]: Setting input delay to: 2.0
[INFO]: Setting load to: 0.01765
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): mprj.clk
Error: Error when finding -clk_nets in DB!

Huh?