I can no longer get through the openlane flow with my design after updating open_pdks to the latest (to resolve missing IO files for the sim). Has anyone else updated and noticed similar?

set_load  $cap_load [all_outputs]

This is the last console log before OpenSTA attempts to allocate seemingly infinite RAM and the inevitable SIGKILL that follows. 32GB of RAM in VM was not enough, where 8GB before was plenty to get through the flow with an otherwise identical design