I'm trying to harden my design and I'm choosing option 2 from (https://github.com/efabless/caravel/blob/master/openlane/README.md) so that I can just plug in my design's verilog files and they're processed as part of the entire flow (e.g., synthesis, STA, CTS, routing, etc). I don't have any macros, just all verilog files. I have a couple of questions: 1.) Do I place my verilog design files under the

VERILOG_FILES

or

VERILOG_FILES_BLACKBOX

? 2.) Do I need to specify the

EXTRA_LEFS

and

EXTRA_GDS_FILES

even though I don't have any macros that are hardened? For this I don't understand why there are LEF and GDS files specified before they're generated. I have removed

add_macro_placement mrpj 1150 1700 N

and

manual_macro_placement f

from the interactive script. Thanks.