#292 Feature Request: vhdl support Issue opened by dhombios Having an open source toolchain for synthesizing integrated circuits can be really useful for research projects. However, some industries enforce the use of vhdl, which is not highly supported by open source projects (the only open source project with similar capabilities that supports vhdl is Electric EDA). Adding vhdl support to this project will allow universities and engineering research centers to reduce dependency on commercial tools and, therefore, making research more accessible. As Openlane is based on Yosis, this could be achievable using the GHDL plugin available for it, which adds support for that language and is also open source. Alternatively, Icarus Verilog provides a vhdl to verilog translator. efabless/openlane