#327 Yosys optimized away an entire design when SYNTH_NO_FLAT=0 Issue opened by KorlaMarch Describe the bug I am running into an issue with Yosys optimizing away my entire design (a modified version of 

user_proj_example

from https://github.com/efabless/caravel_user_project) in the synthesis step. However, the problem went away when I set 

SYNTH_NO_FLAT=1

. I think this is related to the no-driver warning. For instance,

Warning: Wire user_proj_example.\wbs_dat_o [31] is used but has no driver

. But I am not too sure. Logfile from both cases might be helpful: Log Files Good Run (SYNTH_NO_FLAT=1): https://pastebin.com/pfeXFcky Bad Run (SYNTH_NO_FLAT=0): https://pastebin.com/zDCW3iEs To Reproduce Steps to reproduce the behavior: 1. Clone the code from brown-chip/caravel_user_project 2. Setup openlane and caravel 3. remove

set ::env(SYNTH_NO_FLAT) 1

from

openlane/user_proj_conv/runs/user_proj_conv/config.tcl

4. Run

make user_proj_conv

5. Check the error in

openlane/user_proj_conv/runs/user_proj_conv/logs/synthesis/1-yosys.log

Expected behavior

1-yosys.log

should show the synthesis ended with only one multiplexer with

set ::env(SYNTH_NO_FLAT) 0

but show multiple gates and memories with

set ::env(SYNTH_NO_FLAT) 1

Desktop (please complete the following information): • OS: ubuntu • Openlane Version: v0.15 • open_pdks Version: f788cea • skywater-pdk Version: bb2f842 efabless/openlane