Hi, I am making a riscv with small memories. The memories are already being written at system clock frequency. I want to allow management processor to write the program/data to memory. Is it possible to write the program to memory over wishbone interface while top level reset is asserted, wishbone reset is deaaserted, so sequence will be something like ->

Both resets asserted -> Wishbone reset deasserted -> management processor writes program/data to memory over wishbone -> system reset is deasserted -> wishbone clock and reset become dont care to user_project and user_project continues to work on user clock  ?

Thanks