Matthew Guthaus
06/18/2021, 2:51 AMINFO]: Changing netlist from 0 to /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/synthesis/user_project_wrapper.synthesis.v
[INFO]: Running Static Timing Analysis...
[INFO]: current step index: 2
[INFO]: Synthesis was successful
[INFO]: Creating a synthesis netlist with PG pins.
[INFO]: current step index: 3
[INFO]: Running Floorplanning...
[INFO]: Running Initial Floorplanning...
[INFO]: current step index: 4
[INFO]: Core area width: 2908.96
[INFO]: Core area height: 3498.24
[INFO]: Changing layout from 0 to /project/openlane/user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/4-verilog2def_openroad.def