Hello! I see in OpenLane doc that LEC_ENABLE=1 "Enables logic verification using yosys, for comparing each netlist at each stage of the flow with the previous netlist and verifying that they are logically equivalent." Enabling it I see that yosys compares gate netlist after routing whith gate verilog netlist synthesized by yosys from RTL. But how can I be sure that synthesized by yosys gate netlist is equivalent to RTL? Does OplenLane flow have such a check?