Mitch Bailey
08/17/2021, 3:16 AM(no matching pin) |cpu_mask_n[0]
(no matching pin) |ram_ce_e
cpu_mask_n[0] |(no matching pin)
ram_ce_e |(no matching pin)
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Cell pin lists for hs32_core1 and hs32_core1 altered to match.
Cells failed matching, or top level cell failed pin matching.
This from the caravel-Hs32core
of mpw-1. In the schematic here, you can also see that the gate level verilog contains a buffer with a floating output. It looks like the layout is what is intended.
What program outputs the final placement gate level verilog and who is the contact person? Or has this already been fixed?