# openlane

Mitch Bailey

08/17/2021, 3:16 AM
This may be an #openroad question. I've been running LVS on some of the mpw-1 chips and have found that even though the circuit topology and logic are equivalent, the location of pins in buffer chains sometimes differs, i.e. the gate level verilog doesn't match the extracted layout. Here are the final LVS results.
Copy code
(no matching pin)                                             |cpu_mask_n[0]                                                 
(no matching pin)                                             |ram_ce_e                                                      
cpu_mask_n[0]                                                 |(no matching pin)                                             
ram_ce_e                                                      |(no matching pin)                                             
Cell pin lists for hs32_core1 and hs32_core1 altered to match.
Cells failed matching, or top level cell failed pin matching.
This from the
of mpw-1. In the schematic here, you can also see that the gate level verilog contains a buffer with a floating output. It looks like the layout is what is intended. What program outputs the final placement gate level verilog and who is the contact person? Or has this already been fixed?