#579 Incorrect resistor description New issue created by stevvik The SPICE view in sky130A PDK for sky130_fd_sc_hd stdcells library (sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice) contains resistors instantiation with incorrect SPISE syntax. This results in incorrect LVS in OpenLane. In sky130_fd_sc_hd.spice file: .subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO R0 VGND LO VNB sky130_fd_pr__res_generic_po w=480000u l=45000u R1 HI VPWR VNB sky130_fd_pr__res_generic_po w=480000u l=45000u .ends According to SPICE format resistor must have two ports followed by model name, but there are 3 here. Therefore Netgen LVS treats VNB as model name and returns instances mismatch. VNB port must be removed from resistors instantiations, like: .subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO R0 VGND LO sky130_fd_pr__res_generic_po w=480000u l=45000u R1 HI VPWR sky130_fd_pr__res_generic_po w=480000u l=45000u .ends The same resistors are correctly instantiated in other libraries, for example in sky130_fd_io/spice/sky130_fd_io.spice Incorrect instantiations are in sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice and sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice I fixed this in my local PDK copy and LVS passes correctly. The-OpenROAD-Project/OpenLane