Hi all I have a `PLL` IP core in my design which generated t open-source-silicon.dev #openlane

Hi all, I have a `PLL` IP core in my design which...

manili

09/14/2021, 11:37 AM

Hi all, I have a

PLL

IP core in my design which generated the clock of the whole SoC. Now I’d like to know the way I can specify

PLL.CLK_OUT

pin for STA and CTS?