#634 Issue with adding a new design New issue created by akashpatil98 Description Hi, I'm new to the OpenLane flow. I was following the instructions given in the documentation to use the openlane flow for a new design. I've installed OpenLane correctly and even viewed the generated gds files for

make test

to verify the installation. But I'm not able to run it on a new design. Please find the console output below. Environment • Operating System Information:

Linux akash-lenovo 5.4.0-86-generic #97~18.04.1-Ubuntu SMP Sat Sep 18 03:11:22 UTC 2021 x86_64 x86_64 x86_64 GNU/Linux

• Docker Version:

Docker version 20.10.8, build 3967b7d

• OpenLane Tag in use:

2021.09.30_02.12.16

Issue (Console output)

akash@akash-lenovo:~/OpenLane$ sudo make mount
cd /home/akash/OpenLane && \
	docker run -it --rm -v /home/akash/OpenLane:/openLANE_flow -v /home/akash/OpenLane/pdks:/home/akash/OpenLane/pdks -e PDK_ROOT=/home/akash/OpenLane/pdks  --user 0:0 efabless/openlane:2021.09.30_02.12.16
[root@39607478ff50 openLANE_flow]# ./flow.tcl -design my_design -init_design_config
[INFO]: 
	 ___   ____   ___  ____   _       ____  ____     ___
	/   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
	|   | |  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
	| O | |   _/    _]|  |  || |___ |     ||  |  ||    _]
	|   | |  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
	\___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: 2021.09.30_02.12.16
[INFO]: Running non-interactively
[INFO]: Creating design src directory /openLANE_flow/designs/my_design/src
[INFO]: Populating /openLANE_flow/designs/my_design/config.tcl..
[INFO]: Finished populating:
/openLANE_flow/designs/my_design/config.tcl 
Please modify CLOCK_PORT, CLOCK_PERIOD and add your advanced settings to /openLANE_flow/designs/my_design/config.tcl
[SUCCESS]: Done...
[root@39607478ff50 openLANE_flow]# exit
exit

After this, I exited from the docker environment (make mount) to copy

my_design.v

file into

OpenLane/designs/my_design/src

folder. This is to show the file structure inside the new project after copying the verilog file into src folder.

akash@akash-lenovo:~/OpenLane/designs/my_design$ tree -L 2
.
├── config.tcl
└── src
    └── my_design.v

1 directory, 2 files
akash@akash-lenovo:~/OpenLane/designs/my_design$

After this, I again do

sudo make mount

to start the docker environment. Then I proceed with the steps mentioned in the documentation. When I run

./flow.tcl -design my_design

I get an error. Please find the console output below: ``` akash@akash-lenovo:~/OpenLane$ sudo make mount cd /home/akash/OpenLane && \ docker run -it --rm -v /home/akash/OpenLane:/openLANE_flow -v /home/akash/OpenLane/pdks:/home/akash/OpenLane/pdks -e PDK_ROOT=/home/akash/OpenLane/pdks --user 0:0 efabless/openlane:2021.09.30_02.12.16 [root@ec7113bb0028 openLANE_flow]# ./flow.tcl -design my_design [INFO]: _ __ _ __ _ __ __ _ / \ | \ / _]| \ | | / || \ / _] | | | o ) [_ | _ || | | o || _ | / [_ | O | | _/ _]| | || |___ | || | || _] | | | | | [_ | | || || _ || | || [_ \___/ |__| |_____||__|__||_____||__|__||__|__||_____| [INFO]: Version: 2021.09.30_02.12.16 [INFO]: Running non-interactively [INFO]: Using design configuration at /openLANE_flow/designs/my_design/config.tcl [INFO]: Sourcing Configurations from /openLANE_flow/designs/my_design/config.tcl [INFO]: PDKs root directory: /home/akash/OpenLane/pdks [INFO]: PDK: sky130A [INFO]: Setting PDKPATH to /home/akash/OpenLane/pdks/sky130A [INFO]: Standard Cell Library: sky130_fd_sc_hd [INFO]: Optimization Standard Cell Library is set to: sky130_fd_sc_hd [INFO]: Sourcing Configurations from /openLANE_flow/designs/my_design/config.tcl [INFO]: Current run directory is /openLANE_flow/designs/my_design/runs/02-10_05-39 [INFO]: Preparing LEF Files [INFO]: Extracting the number of available metal layers from /home/akash/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef [INFO]: The number of available metal layers is 6 [INFO]: The available metal layers are li1 met1 met2 met3 met4 met5 [INFO]: Merging LEF Files... mergeLef.py : Merging LEFs sky130_ef_sc_hd__fill_12.lef: SITEs matched found: 0 sky130_ef_sc_hd__fill_12.lef: MACROs matched found: 1 sky130_fd_sc_hd.lef: SITEs matched found: 0 sky130_fd_sc_hd.lef: MACROs matched found: 437 sky130_ef_sc_hd__fakediode_2.lef: SITEs matched found: 0 sky130_ef_sc_hd__fakediode_2.lef: MACROs matched found: 1 sky130_ef_sc_hd__fill_8.lef: SITEs matched found: 0 sky130_ef_sc_hd__fill_8.lef: MACROs matched found: 1 sky130_ef_sc_hd__decap_12.lef: SITEs matched found: 0 sky130_ef_sc_hd__decap_12.lef: MACROs matched found: 1 mergeLef.py : Merging LEFs complete [INFO]: Trimming Liberty... [INFO]: Generating Exclude List... [INFO]: Storing configs into config.tcl ... [INFO]: Preparation complete [INFO]: Running Synthesis... [INFO]: current step index: 1 /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+4052 (git sha1 d061b0e, gcc 8.3.1 -fPIC -Os) [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. 1. Executing Verilog-2005 frontend: /openLANE_flow/designs/my_design/src/my_design.v ERROR: No such module: my_design [ERROR]: during executing: "yosys -c /openLANE_flow/scripts/synth.tcl -l /openLANE_flow/designs/my_design/runs/02-10_05-39/logs/synthesis/1-yosys.log |& tee >&@stdout" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child process exited abnormally [ERROR]: Please check yosys log file [ERROR]: Dumping to /openLANE_flow/designs/my_design/runs/02-10_05-39/error.log [INFO]: Calculating Runtime From the Start... [INFO]: flow failed for my_design/02-10_05-39 in 0h0m4s [INFO]: Generating Final Summary Report... [INFO]: Design Name: my_design Run Directory: /openLANE_flow/designs/my_design/runs/02-10_05-39 Source not found. ---------------------------------------- LVS Summary: Source: /openLANE_flow/designs/my_design/runs/02-10_05-39/results/lvs/my_design.lvs_parsed.gds.log Source not found. -… The-OpenROAD-Project/OpenLane