#658 CTS:: run_resizer_timing stage over-write the Synthesis netlist New issue created by dineshannayya During Synthesis Output => results/synthesis/_.synthesis_optimized.v CTS :: run_cts stage Output => results/synthesis/_.synthesis_cts.v CTS :: "run_resizer_timing" Output=> results/synthesis/*.synthesis_optimized.v <= This over-write the Previous Synthesis netlist The issue look to be due to File: scripts/tcl_commands/placement.tcl proc run_resizer_timing {args} { ... ... write_verilog $::env(yosys_result_file_tag)_optimized.v } Due this issue, Re-Running Only CTS Step once again is not working. The-OpenROAD-Project/OpenLane