#718 Support for overriding the module parameter during synthesis New issue created by dineshannayya Prompt When Generic IP which has multiple parameter over-ride option, it would be better to provide module parameter over-ride during synthesis. Yosys support command to overide the module parameter. HERE is Yosys Example command Memory bits <= 18K; Data width <= 36; Address width <= 14: read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 blockram This module parameter option is not supported in Openlane flow. Proposal Add additional environmental variable like : SYNTH_PARAMS set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 8, BIST_DATA_WD 32, BIST_ADDR_START 9'h000, BIST_ADDR_END 9'h1FB, BIST_REPAIR_ADDR_START 9'h1FC, BIST_RAD_WD_I 9, BIST_RAD_WD_O 9 " Add the following logic in synth.tcl & synth_top.tcl Module level parameter overide if { [info exists ::env(SYNTH_PARAMS) ] } { log "Reading $::env(SYNTH_PARAMS) as a parameter" set records [split $::env(SYNTH_PARAMS) ","] foreach rec $records { chparam -set [lindex $rec 0] [lindex $rec 1] $vtop } } else { log "No parameter define found" } synth.txt synth_top.txt Attached the modified scripts/synth.tcl and scripts/synth_top.tcl Note: File name extension is changes from .tcl to .txt due to github attach error/ Alternatives Currently we have to manually hardcode the paremeter inside the generic module. The-OpenROAD-Project/OpenLane