<#784 Timing Signoff: SS corner seems to be the wo...
# openlane
g
#784 Timing Signoff: SS corner seems to be the worst-case corner for hold violations New issue created by msaligane Description We have noticed during the timing validation of the LiteX management core that min timing checks has an unexpected trend where
sky130_fd_sc_hd__ss_100C_1v60.lib
seems to be showing the worst case slack. Based on my checks of the openlane flow, the following libs are used for multi-corner checks:
Copy code
sky130_fd_sc_hd__ss_100C_1v60.lib
sky130_fd_sc_hd__ff_n40C_1v95.lib
sky130_fd_sc_hd__tt_025C_1v80.lib
We have compiled the timing reports in the following table:

image

Similarly, as a sanity check, we have ran the AES design from openlane's design suite regression tests. We noticed the same behavior:

image

Environment
Copy code
---                                                                                                                 Git Log (Last 3 Commits)                                                                                                                                                                                                                commit 96a630e29c60f47d87c63642e2af39c19a48cdb7                                                                     Author: Vitor Bandeira <vvbandeira@users.noreply.github.com>                                                        Date:   Tue Dec 21 21:37:30 2021 -0300                                                                                                                                                                                                      Improve Jenkins pipeline (#782)                                                                                                                                                                                                         - clean before checkout                                                                                             - fix stage names                                                                                                   - add back designs                                                                                                                                                                                                                      Signed-off-by: Vitor Bandeira <vitor.vbandeira@gmail.com>                                                                                                                                                                               [skip ci]                                                                                                                                                                                                                           commit 1ab8d55fab363b9e10b08111a9ee14954f65e3ef                                                                     Author: Donn <me@donn.website>                                                                                      Date:   Wed Dec 22 02:36:50 2021 +0200                                                                                                                                                                                                      Fix or Remove Designs Failing The Extended Test Set (#777)                                                                                                                                                                              + Added ability to run extended test sets on a specific pull request's PR by adding `[ci ets]` anywhere in the PR body (the example there counted!)                                                                                     + Added capacity to disable certain designs in a test set by prefixing the design with a `#`                        + Added new script that allows someone to iterate on a design's timing closure                                      ~ Decreased core utilization for some designs that just aren't routing                                              ~ Fixed sizes of {BM64, blabla, y_huff} to avoid pin location issue                                                 ~ Increased max buffer percentages for some designs failing to achieve timing closure                               ~ Update all references to the design directory in config.tcl for all designs to `$::env(DESIGN_DIR)`.              ~ core area/die area no longer have an EOL at the end of their value                                                                                                                                                                commit 86a5e29c4f9126920174dc2f2e43a1348c743a83                                                                     Author: Donn <me@donn.website>                                                                                      Date:   Tue Dec 21 20:52:09 2021 +0200                                                                                                                                                                                                      Update Documentation for `or_issue.py` (#780)                                                                                                                                                                                           [skip ci]
Reproduction Material The design is available in github here (with tar balls and all): https://github.com/efabless/caravel_mgmt_soc_litex/releases Expected behavior I expect the min timing checks reports to fail for the
ff_n40C_1v95
corner or show worst violating slack compared to the
ss_100C_1v60
corner. @mkkassem FYI. The-OpenROAD-Project/OpenLane