# openlane

Olof Kindgren

12/28/2021, 9:41 PM
Ok, so now I see where my slew time violations are. The question that remains is how to fix them. I guess there is something that automatically inserts buffers on high fanout nets. And since this is a clock signal, I also assume CTS has some logic to decide when to place clock buffers (I see 8 clock buffers in series on the path to the point of failure). On top of that I suspect inserted diodes affect slew rate too. To me, this looks like it would need an interative solution where timing analysis is part of the loop. Looking here however it seems like the STA is outside this loop, which means that timing results are not fed back to subsequent iterations