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#openlane
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# openlane
m

Maximo Balestrini

01/12/2022, 6:58 PM
Is there a way right now for the flow to use a macro's verilog and spef file when running the design STA? So it can modify the parent design to meet the timings? In my project I was using a DFFRAM macro that I didn't realize was causing HOLD violations until I run a STA script on the full hierarchy I think it would be good to be able to use the inserted macro spef if you have it