Tapeout Signoff Workshop - Physical Verification u...
# general
Tapeout Signoff Workshop - Physical Verification using Skywater 130nm Toughest Semiconductor Workshop on planet - Physical Verification using Skywater 130nm technology has now been simplified and ready for deployment. This would not have been possible without relentless support and dedication by @User @User, Founder Open Circuit Design and SVP at Efabless​ .He is analog VLSI designer and has been collecting and developing open-source EDA tools for over 27 years. Most of you might know him if you have used qflow and Magic. In short, VSD foundation is based on open-source and @User plays a very critical role in opensource semi-conductor industry Physical Verification using Skywater 130nm technology workshop intends to address various issues that come up during the design cycle as DRC/LVS violations. It aims to demonstrate the best approach to mitigate and rectify these violations. The course covers Physical Verification methodology using Magic,Netgen and OpenLane flow. It also explores the SKY130 PDK in detail, the knowledge of which is necessary to generate a robust design. This course starts with giving the basic idea of the design flow, PDK libraries and then takes a deep dive into the intricate concepts of Physical Verification with dedicated lecture and labs for each topic. If you are looking to manufacture and tape-out your own chip, you just can't skip DRC/LVS and other crucial physical verification sign-off checks. Below is the registration link (Workshop date 11th -15th August) which has the curriculum and closes in 6-days https://www.vlsisystemdesign.com/physical-verification-using-sky130/ So all the best and happy learning
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