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#riscv
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# riscv
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Ernest Seah

07/27/2020, 1:40 PM
Hi, has the documentation for the RISC-V in the test harness been published somewhere? I'm trying to store a 64kx16 image in the SPI that can be loaded via a dual-port SRAM to the end-user memory, and am trying to determine how to interface them. Also, what clocks are available from the RISC-V or should I plan to have my own clock input? Thanks.
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