Matthew Guthaus
06/14/2021, 8:58 PMWARNING STA-0337] port 'clk' not found.
[INFO]: Setting output delay to: 3.0
[INFO]: Setting input delay to: 3.0
[WARNING STA-0337] port 'clk' not found.
[INFO]: Setting load to: 0.01765
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s):
[INFO]: Running Clock Tree Synthesis...
*****************
* TritonCTS 2.0 *
*****************
*****************************
* Create characterization *
*****************************
Number of created patterns = 50000.
Number of created patterns = 100000.
Number of created patterns = 150000.
Number of created patterns = 200000.
Number of created patterns = 250000.
Number of created patterns = 300000.
Number of created patterns = 313632.
Compiling LUT
Min. len Max. len Min. cap Max. cap Min. slew Max. slew
2 8 1 39 1 298
[WARNING] 6336 wires are pure wire and no slew degration.
TritonCTS forced slew degradation on these wires.
Num wire segments: 313200
Num keys in characterization LUT: 2033
Actual min input cap: 2
**********************
* Find clock roots *
**********************
User did not specify clock roots.
************************
* Populate TritonCTS *
************************
Initializing clock nets
Looking for clock nets in the design
[ERROR UKN-0000] No clock nets have been found.