@User In OpenRoad, do the CLOCK_NETS need to be ports to modules? If I give a net to clock_tree_synthesis (through OpenLane), it seems to fail with: A similar question exists for STA... There are cases where we may gate a clock or select from multiple inputs but still want to route it like a clock tree or perform STA using it as the clock. Sorry, asking here since this seems to be more of an OpenRoad question than OpenLane. This is what I get when I specify it:

WARNING STA-0337] port 'clk' not found.                                                                                                                         
[INFO]: Setting output delay to: 3.0                                                                                                                             
[INFO]: Setting input delay to: 3.0                                                                                                                              
[WARNING STA-0337] port 'clk' not found.                                                                                                                         
[INFO]: Setting load to: 0.01765                                                                                                                                 
[INFO]: Configuring cts characterization...                                                                                                                      
[INFO]: Performing clock tree synthesis...                                                                                                                       
[INFO]: Looking for the following net(s):                                                                                                                        
[INFO]: Running Clock Tree Synthesis...                                                                                                                          
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 * TritonCTS 2.0 *                                                                                                                                               
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 *  Create characterization  *                                                                                                                                   
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Number of created patterns = 50000.
Number of created patterns = 100000.
Number of created patterns = 150000.
Number of created patterns = 200000.
Number of created patterns = 250000.
Number of created patterns = 300000.
Number of created patterns = 313632.
 Compiling LUT
    Min. len    Max. len    Min. cap    Max. cap   Min. slew   Max. slew
           2           8           1          39           1         298
    [WARNING] 6336 wires are pure wire and no slew degration.
    TritonCTS forced slew degradation on these wires.
    Num wire segments: 313200
    Num keys in characterization LUT: 2033
    Actual min input cap: 2
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 *  Find clock roots  *
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 User did not specify clock roots.
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 *  Populate TritonCTS  *
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 Initializing clock nets
 Looking for clock nets in the design
[ERROR UKN-0000] No clock nets have been found.