Is there is way to override the module parameter during yosys synthesis? I see yosys support , chparam command to overide the module parameter, I don't see Openlane synth script uses this command ? #### HERE is Yosys Example command ###################### # Memory bits <= 18K; Data width <= 36; Address width <= 14: read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp