02/19/2023, 11:00 AM
Hey guys. I am new to this community and I am still trying to understand what is possible to do with this process. I have a design that I have implemented on an FPGA, which depends on UART and a 100 MHZ clock. I am trying to understand whether such a design would be possible to tape out with this process.

Luis Henrique Rodovalho

02/19/2023, 11:18 AM The Caravel harness has an internal PLL with maximum 214 MHz. You could use it, but I'm not sure your design could run at those speeds. This document says 50 MHz is guaranteed across all PVT corners.

Tim Edwards

02/20/2023, 9:21 PM
The Caravel processor (the VexRISC) runs at 50 MHz (although I think the actual number is more like 40), although you might consider it typical for what the tools can achieve on a design of that complexity. That does not dictate what the user design must run at, although any part of the user design that communicates with the processor through wishbone needs to be synced to the processor's clock. A design that is streamlined for speed can probably hit 100MHz, but it really depends on the design. Bear in mind that the I/O pads are (officially) limited to 50MHz. You might be able to get a 100MHz clock across one, but you're better off either using the internal DLL (as Luis mentioned) (which does not reach the original intended 214 MHz but will easily hit 100 MHz), or creating a clock doubler.