I'm struggling to get

make verify-mprj_por

to run on the caravel_user_project_analog repository. This is the output of

make verify-mprj_por

docker run -v /home/aidenp/Documents/caravel_user_project_analog:/home/aidenp/Documents/caravel_user_project_analog -v /home/aidenp/pdk:/home/aidenp/pdk \
        -v /home/aidenp/Documents/caravel_user_project_analog/caravel:/home/aidenp/Documents/caravel_user_project_analog/caravel \
        -e TARGET_PATH=/home/aidenp/Documents/caravel_user_project_analog -e PDK_ROOT=/home/aidenp/pdk \
        -e CARAVEL_ROOT=/home/aidenp/Documents/caravel_user_project_analog/caravel \
        -u : efabless/dv_setup:latest \
        sh -c "cd /home/aidenp/Documents/caravel_user_project_analog/verilog/dv/mprj_por && export SIM=RTL && make"
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -I /home/aidenp/Documents/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/opt/riscv32i/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex 
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -DEF_STYLE -I /home/aidenp/pdk/ \
-I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp 
/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl/caravan_netlists.v:30: Include file libs.ref/verilog/sky130_fd_io/sky130_fd_io.v not found
../../../verilog/rtl/example_por.v:57: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:68: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:79: error: Unknown module type: sky130_fd_sc_hvl__lsbufhv2lv_1
../../../verilog/rtl/example_por.v:57: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:68: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:79: error: Unknown module type: sky130_fd_sc_hvl__lsbufhv2lv_1
7 error(s) during elaboration.
*** These modules were missing:
        sky130_fd_sc_hvl__lsbufhv2lv_1 referenced 2 times.
        sky130_fd_sc_hvl__schmittbuf_1 referenced 4 times.
***
make: *** [Makefile:51: mprj_por.vvp] Error 7
rm mprj_por.elf
make: *** [Makefile:61: verify-mprj_por] Error 2

This github issue has the same issue as me and provides a partial solution: https://github.com/efabless/caravel_user_project_analog/issues/29 but after I modify the makefile to export

PDK

I get another error:

docker run -v /home/aidenp/Documents/caravel_user_project_analog:/home/aidenp/Documents/caravel_user_project_analog -v /home/aidenp/pdk:/home/aidenp/pdk \
        -v /home/aidenp/Documents/caravel_user_project_analog/caravel:/home/aidenp/Documents/caravel_user_project_analog/caravel \
        -e TARGET_PATH=/home/aidenp/Documents/caravel_user_project_analog -e PDK_ROOT=/home/aidenp/pdk \
        -e CARAVEL_ROOT=/home/aidenp/Documents/caravel_user_project_analog/caravel -e PDK=sky130A \
        -u : efabless/dv_setup:latest \
        sh -c "cd /home/aidenp/Documents/caravel_user_project_analog/verilog/dv/mprj_por && export SIM=RTL && make"
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -I /home/aidenp/Documents/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/opt/riscv32i/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex 
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/aidenp/pdk/sky130A \
-I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp 
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl/caravan_netlists.v:97: Include file mgmt_core_wrapper.v not found
vvp mprj_por.vvp

I've tried running

make install_mcw

and exporting

MCW_ROOT

to docker in the makefile, but that doesn't fix the issue. Does anybody know how to fix this or if there is another version of caravel_user_project_analog that would work?

@Aiden Petersen Sounds like you’re getting close! Just some general suggestions. The Makefile in

caravel_user_project

is probably better supported. You might want to check the differences to the one you’re using. You probably need to include the MCW_ROOT verilog directory in the

iverilog

command.

@Aiden Petersen: The Makefile in caravel_user_project_analog looks very out-of-date with respect to what's in caravel_user_project. As Mitch said, though, you do seem to be close. Iverilog cannot find the managment core wrapper, and it looks like that's because there's no

-I

include path for it passed to iverilog. Try adding to

verilog/dv/mprj_por/Makefie

line 52

-I $(MCW_ROOT)/verilog/rtl

.

Thanks for the help. I'm getting a new error after I implemented your change.

docker run -v /home/aidenp/Documents/caravel_user_project_analog:/home/aidenp/Documents/caravel_user_project_analog -v /home/aidenp/pdk:/home/aidenp/pdk -v /home/aidenp/Documents/caravel_user_project_analog/mgmt_core_wrapper:/home/aidenp/Documents/caravel_user_project_analog/mgmt_core_wrapper\
        -v /home/aidenp/Documents/caravel_user_project_analog/caravel:/home/aidenp/Documents/caravel_user_project_analog/caravel \
        -e TARGET_PATH=/home/aidenp/Documents/caravel_user_project_analog -e PDK_ROOT=/home/aidenp/pdk \
        -e CARAVEL_ROOT=/home/aidenp/Documents/caravel_user_project_analog/caravel -e PDK=sky130A -e MCW_ROOT=/home/aidenp/Documents/caravel_user_project_analog/mgmt_core_wrapper \
        -u : efabless/dv_setup:latest \
        sh -c "cd /home/aidenp/Documents/caravel_user_project_analog/verilog/dv/mprj_por && export SIM=RTL && make"
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -I /home/aidenp/Documents/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/opt/riscv32i/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex 
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/aidenp/pdk/sky130A \
-I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
-I /home/aidenp/Documents/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp 
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/aidenp/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/aidenp/Documents/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:289: error: Unknown module type: buff_flash_clkrst
/home/aidenp/Documents/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl/mgmt_core_wrapper.v:150: error: Unknown module type: mgmt_core
512 error(s) during elaboration.
*** These modules were missing:
        buff_flash_clkrst referenced 1 times.
        mgmt_core referenced 1 times.
***
vvp mprj_por.vvp
mprj_por.vvp: Unable to open input file.
make: *** [Makefile:65: mprj_por.vcd] Error 255
rm mprj_por.elf
make: *** [Makefile:61: verify-mprj_por] Error 2

I was able to get rid of the buff_flash_clkrst error by modifying the caravan netlist, but more missing components pop up.

It looks like the simulation environment in

caravel_user_project_analog

is broken. @Marwan Abbas (@Kareem Farid, @mshalan), can you please comment on this?

Should be fixed in PR https://github.com/efabless/caravel_user_project_analog/pull/42

@Marwan Abbas: Is that pull request merged yet?

Not yet, waiting for your review

I started the morning with back-to-back meetings and haven't even checked my email yet, so I didn't see the review request. I'll get on it now.