Hi I want to share this, was useful to debugging one pin making bad connection. If you see any error or suggestion just comment.

I've been looking for something similar for the nucleo hat board. My eyes can barely see the silk screen so I need to use a camera + zoom 🙂 Anyone have a diagram of the nucleo hat board pins?

I was planning also to do something similar for the hat xD

I just keep a magnifying glass handy. . . : )

I need to buy one. It reminds me that I need to get my eyes checked as well.

. . . And it's not like I didn't specifically tell the PCB designer, several times, that all silkscreen needs to be large enough to be readable. An extra few millimeters on each side of the board costs nothing. Also, the I/Os are in order around the edge of the daughterboard, so why are they so scrambled on the Nucleo pins? Obviously some pins have to be avoided, but it seems like the I/O should have been able to be placed more or less sequentially.

Thanks @Ivan Rodriguez That's extremely helpful.

Hi this is the first version for the nucleo hat. If you discover any issue or any suggestion just tell me.

thanks for making these diagrams, I found them really helpful! @Tim Edwards @Ivan Rodriguez @jeffdi Where can I find the mapping between these mprj_io pin numbers and the pin names in user_project_wrapper (e.g., io_in, io_out, analog_io, etc.)? I was looking here https://github.com/efabless/caravel_user_project/blob/main/verilog/rtl/user_project_wrapper.v and it seems like the mprj pins correspond to multiple internal pins (since io_in, io_out, and io_oeb all have MPRJ_IO_PADS = 38)?