@jeffdi @Tim Edwards I made this small flow chart for my understanding on what files are being used to load a program and also the flow of how a program is loaded to the caravel. Please correct me if I have made any mistakes in the same. Also I wanted to understand what the

reg_mprj_xfer

register maps to since all the generated configuration data is being written to the same. Thank you for all the help!

Yes, that's an accurate flowchart. Thanks for the contribution! Our preferred method for the last step is not

pyftdi

+

caravel_hkflash.py

, though, but

mpremote

+

flash.py

---But this is essentially equivalent, as you can see if you compare

flash.py

(in the nucleo/ directory) against

caravel_hkflash.py

(in the util/ directory); the former is a copy of the latter, modified to use the Nucleo pins to drive the housekeeping SPI. There are two methods for configuring the GPIO. By far, the easiest one is to set bit 0 of

reg_mprj_xfer

, which initiates the automatic configuration that pulls the data from

reg_mprj_io_*

and passes it to the GPIO control blocks. Then there is the "emergency backup system" which can be used to bit-bang the same system. This system is entirely unnecessary for programming the part, but was extremely helpful for figuring out the problem with the independent and dependent hold violations. For some reason I cannot convince Jeff and Marwan to use the simpler method, which is why this flowchart and the code are ridiculously convoluted. The bit-bang controls are in the same register as the transfer initiation bit, so the register looks like:

bit:   7       6           5          4       3       2        1       0
       0    data_left   data_right   clock   load   resetn   enable   xfer

The

data_left

goes to the left side shift register (GPIO 37 to 19), and

data_right

goes to the right side shift register (GPIO 0 to 18). The control bits

clock

,

load

,

resetn

, and

enable

should be self-explanatory. Either 12 or 13 clock pulses are needed per GPIO, depending on whether the GPIO has an independent hold violation in front of it (12 bits) or not (13 bits).

Thanks a lot for the explanation! Really helps in understanding what is actually happening during the GPIO configuration.

It'd awesome to get the flow chart added to the repo!