open-source-silicon.dev

is there a way to make magic matches port ordering from an existing spice netlist during extraction? (i.e: having it parse the .spice file) or does one should carefully craft matching `port` definition with explicit index in an extraction script?

Sometimes I change the .mag file directly. Sometimes I just give up and change the spice netlist.

<@U02Q5NCBMC5> A relatively simple solution might be to use a subckt wrapper.
Normal source netlist
```.SUBCKT TOP A B C D 
...
.ENDS```
Extacted netlist
```.SUBCKT TOP D C A B
...
.ENDS```
Like this you can’t swap the extracted netlist for the source netlist because the ports are in the wrong order.
However, if you rename the extracted netlist (e.g. TOP_ext) and use a wrapper, you can
```.SUBCKT TOP_ext D C A B
...
.ENDS
.SUBCKT TOP A B C D
X0 D C A B TOP_ext
.ENDS```

seems that doing some `port NAME index NUMBER`

before running the extract does the trick

Stop having long discussions while I'm sleeping. . .   I have a direct and simple answer for you!  : )

The answer is that you can use the scripted command `readspice` to make all the pins match a netlist.  See the documentation:
<http://opencircuitdesign.com/magic/commandref/readspice.html>

<@U01QTMG2K8R>:  It's much harder to renumber instances, because that implies knowing which instances are which, and that implies running (and passing) LVS.  One possibility would be to have netgen dump a complete list of matching net names, instance names, and pin names, and use that output file to annotate any of the three.

Is there a way to name a custom made transistor inside a cell before extracting it?

Place a label on top of the gate and give it a name ending with the character `^`.  That will become the transistor instance name.

e.g., the label `20^` should generate device `X20`.