I noticed that there is already a 11K variant in t...
# gf180mcu
I noticed that there is already a 11K variant in the PDK packaged by open_pdks:
I could recast
as having an 1.1um thick top metal, but since we taped out the first MPW run with a 0.9um thick top metal, it's better to leave that one as-is and just specify a new variant called
for the 5-metal stack with 1.1um thick top metal. It's trivial to do in open_pdks, which is designed to be configurable for any possible stack (at least the parts of the PDK that I wrote are configurable in that way).
Cool! I can try to send the change for that :)
oh @jeffdi already created an issue for this here https://github.com/RTimothyEdwards/open_pdks/issues/342
@proppy we will need to add that to the DRC as well
We need a PR for that.
@Amro Tork the techlef for the standard cell and the drc decks look similar.
I suspect we need to also update parasitics extraction for magic (@Tim Edwards?) and openrcx enablement (@Tom Spyrou?) to account for the new 11K variant.
We were musing with @mehdi if it should affect timing at all, since it seems that the top layer is mainly used for power delivery.
The top layer is a valid routing layer so unless disallowed in the router setup it can be used.
For power grid signoff the top layer needs to be extracted as well.
@proppy: Typically, a standard cell layout of the complexity of a microcontroller, especially with components like multi-bit adders, multipliers, and barrel shifters, all of which are mostly combinatorial logic, will require four routing layers, two full layers (one vertical and one horizontal) over the whole layout area with no obstructions, and two additional layers (one vertical and one horizontal) for long trunk routes and to take up the overload when the lower layers get too congested. The upper two layers can overlap the power supply layers. That's not ideal, but it makes it possible to do routing with fewer layers. The sky130 process is pretty good for this: The standard cells are routed mainly with local interconnect, and point-to-point routes between neighboring cells can be done with local interconnect. There is room between the power rails for metal 1 routes, then metals 2 and 3 are completely free of obstructions, metal 4 overlaps with the lower power grid, and metal 5 can be used almost exclusively for the power grid. The GF180MCU with a 5 metal stack is harder, and it's made worse by the fact that most standard cell pins are completely blocked in by metal 1, so that point-to-point routes between neighboring cells have to go up to metal 2 and use up metal 2 resources. So metals 2 and 3 are free for routing (but more congested than usual because of the lack of metal 1 routes), but all the overflow will have to be done on metals 4 and 5, threading among the power supply straps. Therefore there is quite a lot of routing on these layers. Also, yes, the parasitics need to be updated for the 1.1um thick metal.