@proppy: Typically, a standard cell layout of the complexity of a microcontroller, especially with components like multi-bit adders, multipliers, and barrel shifters, all of which are mostly combinatorial logic, will require four routing layers, two full layers (one vertical and one horizontal) over the whole layout area with no obstructions, and two additional layers (one vertical and one horizontal) for long trunk routes and to take up the overload when the lower layers get too congested. The upper two layers can overlap the power supply layers. That's not ideal, but it makes it possible to do routing with fewer layers. The sky130 process is pretty good for this: The standard cells are routed mainly with local interconnect, and point-to-point routes between neighboring cells can be done with local interconnect. There is room between the power rails for metal 1 routes, then metals 2 and 3 are completely free of obstructions, metal 4 overlaps with the lower power grid, and metal 5 can be used almost exclusively for the power grid. The GF180MCU with a 5 metal stack is harder, and it's made worse by the fact that most standard cell pins are completely blocked in by metal 1, so that point-to-point routes between neighboring cells have to go up to metal 2 and use up metal 2 resources. So metals 2 and 3 are free for routing (but more congested than usual because of the lack of metal 1 routes), but all the overflow will have to be done on metals 4 and 5, threading among the power supply straps. Therefore there is quite a lot of routing on these layers.
Also, yes, the parasitics need to be updated for the 1.1um thick metal.