Are there any simple Verilog models of DFFRAM? I n...
# dfframs
Sean Cross
02/13/2023, 10:59 AMAre there any simple Verilog models of DFFRAM? I notice that generating a file produces something that can generate a testbench, but that seems like a full simulation. I'm looking for a simple functional model that I can run my design against that just implements this spec: https://github.com/AUCOHL/DFFRAM/blob/main/docs/md/Specs.md#ram-1rw1r-interface
Sean Cross
02/13/2023, 11:46 AMI threw together a simple model that seems to pass tests:
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verilog
module RAM32_1RW1R #(parameter USE_LATCH=1,
WSIZE=1 )
(
input wire CLK, // FO: 4
input wire [WSIZE-1:0] WE0, // FO: 4
input EN0, // FO: 4
input EN1, // FO: 4
input wire [4:0] A0, // FO: 1
input wire [4:0] A1,
input wire [(WSIZE*8-1):0] Di0, // FO: 4
output wire [(WSIZE*8-1):0] Do0,
output wire [(WSIZE*8-1):0] Do1
);
reg [31:0] backing[31:0];
// Look up register file contents combinatorially
assign Do0 = backing[A0];
assign Do1 = backing[A1];
always @(negedge CLK) begin
// writeback
if (WE0[0]) begin
backing[A0][7:0] <= Di0[7:0];
end
if (WE0[1]) begin
backing[A0][15:8] <= Di0[15:8];
end
if (WE0[2]) begin
backing[A0][23:16] <= Di0[23:16];
end
if (WE0[3]) begin
backing[A0][31:24] <= Di0[31:24];
end
end
endmodule12 Views