verilog
module RAM32_1RW1R  #(parameter    USE_LATCH=1,
                                    WSIZE=1 ) 
(
    input   wire                    CLK,    // FO: 4
    input   wire [WSIZE-1:0]        WE0,     // FO: 4
    input                           EN0,     // FO: 4
    input                           EN1,     // FO: 4
    input   wire [4:0]              A0,     // FO: 1
    input   wire [4:0]              A1,
    input   wire [(WSIZE*8-1):0]    Di0,     // FO: 4
    output  wire [(WSIZE*8-1):0]    Do0,
    output  wire [(WSIZE*8-1):0]    Do1  
);

  reg [31:0] backing[31:0];

  // Look up register file contents combinatorially
  assign Do0 = backing[A0];
  assign Do1 = backing[A1];

  always @(negedge CLK) begin
    // writeback
    if (WE0[0]) begin
      backing[A0][7:0] <= Di0[7:0];
    end
    if (WE0[1]) begin
      backing[A0][15:8] <= Di0[15:8];
    end
    if (WE0[2]) begin
      backing[A0][23:16] <= Di0[23:16];
    end
    if (WE0[3]) begin
      backing[A0][31:24] <= Di0[31:24];
    end
  end
endmodule