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Hi, I'm seeing the following DRC issue inside the RAM32x32 (possibly the other ones as well):
`All nwells must contain metal-connected N+ taps (nwell.4)`

<@U01634FH82K> <@U020J2W6Q84> have you checked drc on your end? is this an issue with my drc setup?

I will be looking at this shortly. Stay tuned.

image.png

Hello <@U01RNKP9R0B>, I am working alongside <@U020J2W6Q84> and dr <@U01634FH82K> on the dffram compiler project. I just ran the flow with 32x32 size and it terminates without drc issues (included a screenshot)

1- Please `git pull origin main`
2- update your pdk

the command I used is : `./prflow.py -s 32x32 -p $PDK_ROOT` , `$PDK_ROOT` is where your `sky130A` pdk resides

We do run DRC as part of our flow. This is new. Which version of DFFRAM are you using? What's your command?

The easiest way to update your `sky130A`  pdk is to clone openlane :
1-  `git clone <https://github.com/The-OpenROAD-Project/OpenLane>` 
2-  `cd openlane`
3-  `PDK_ROOT=&lt;YOUR PREFERED LOCATION FOR THE PDK&gt; make pdk`

the compiler is a week or two old, will update and retry

just to make sure, are you checking drc on the gds with magic?

I just used the updated compiler and ran the drc on the gds with magic and it has some violations.

RAM32.drc

<@U01RNKP9R0B> <@U023UDNU0SE> We’re investigating- we do run DRC with Magic as part of prflow, so it’s curious that there are tapping issues.

Hi <@U020J2W6Q84> <@U021B0144M6>, just wanted to follow up to see if you guys had any updates

<@U01RNKP9R0B> <@U023UDNU0SE> We’ve isolated the issue and we’re working on it. We appreciate your patience.

<@U01RNKP9R0B> <@U023UDNU0SE> The issue has in addressed. Thank you for your patience.