Hello. I am getting the error in CTS, I have inter...
# openlanem
M_Naveed_Abbasi
02/11/2023, 12:08 PMHello. I am getting the error in CTS, I have interfaced a simple Counter module with the caravel user project. What is the reason for this error? I have attached all the files in the RTL folder. I may be defining the Clock wrong. Kindly verify, If anyone has faced a similar error.
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Vijayan Krishnan
02/11/2023, 12:53 PMdo you got any
issue_reproducibleVijayan Krishnan
02/11/2023, 12:55 PMfile an issue here: https://github.com/The-OpenROAD-Project/OpenLane/issues and testcase can be generated by following: https://openlane.readthedocs.io/en/latest/for_developers/using_or_issue.html#manually
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M_Naveed_Abbasi
02/11/2023, 1:23 PMissue_reproducible , >> NO.
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manili
02/11/2023, 3:03 PMHey Naveed,
Which module are you running OL at, right now? Is it the wrapper or the counter? I guess you are pointing to a wrong signal “address” as your clock.
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M_Naveed_Abbasi
02/11/2023, 8:18 PMI used the command make count_test
M_Naveed_Abbasi
02/11/2023, 8:28 PMuser_project_wrapper Error
M_Naveed_Abbasi
02/11/2023, 10:11 PMThanks for the reply it's working, Now, I need to figure out HOW to WRITE Code for RISC V in C, Kindly Send RISC V manual. I have experience using STM 32 and Arduino. But STM there are plenty of templates like how to control pins etc. Any one have resources for This too? Kindly share. Thanks
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manili
02/12/2023, 8:16 PM@M_Naveed_Abbasi
You might find this helpful (just as an example to write your test/c-code):
https://github.com/manili/vsdmemsoc_mpw3/tree/main/verilog/dv/la_test
manili
02/12/2023, 8:19 PMNote that this code has been written for MPW3, so you need to recheck the updated docs about the Caravel.
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M_Naveed_Abbasi
02/12/2023, 8:31 PMThanks, I have this one. I need more detail doc.
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manili
02/12/2023, 10:06 PMThe link includes a lot of details which took me several days to find and then write the code.
BTW, I hope you find the following links helpful:
1. https://caravel-user-project.readthedocs.io/en/latest/#gpio-configuration
2. https://caravel-harness.readthedocs.io/en/latest/
3. https://caravel-harness.readthedocs.io/en/latest/getting-started.html
4. https://caravel-harness.readthedocs.io/en/latest/memory-mapped-io-summary.html
5. https://caravel-harness.readthedocs.io/en/latest/irq.html
6. https://github.com/YosysHQ/picorv32
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M_Naveed_Abbasi
02/13/2023, 8:38 AMThank you So much.....
👍🏻 1
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Matt Liberty
02/13/2023, 6:59 PMwhat are you specifying for -clk_nets - it seems like the named nets doesn't exist in your netlist
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M_Naveed_Abbasi
02/16/2023, 2:59 PM Copy code
wb_clk_i used this Clock .M_Naveed_Abbasi
02/16/2023, 3:03 PMI have defined it in User_Project_Wrapper. Why I am getting errors. Check attached image
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Vijayan Krishnan
02/17/2023, 6:59 AMshare your config.json
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M_Naveed_Abbasi
02/21/2023, 6:54 PMHow I can generate .lef files for my design. images are attached. (method_1) I have synthesized my design by putting RTL in the user_proj_example and used (make user_project_wrapper ) Worked Fine / had No issues. (method_2) But when I try to synthesize using make user_project_wrapper I get errors. (in this case, I instantiated my design in the user_project_wrapper).
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Vijayan Krishnan
02/22/2023, 6:08 AMlef/counter_test.lefm
M_Naveed_Abbasi
02/22/2023, 5:10 PMyes, you are 100% right the file is not available. But to generate this file for my design?
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manili
02/23/2023, 7:43 PMNaveed
It seems like you’re getting some errors during the OenLane’s flow and it doesn’t finish successfully, right? AFAIK in this case you won’t get any “final” products (including the LEF file).
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M_Naveed_Abbasi
02/23/2023, 11:11 PMyes, OpenLane’s flow gets fail. But user_project_wrapper works fine.