Hi, I have done DC analysis of NMOS setup vdd(Vds) = 1.8v, Vgs vary form 0 to 1.8v 1. Width = 40 um, multiplier = 7 and finger = 1 and Length = .5um @1.5 V(Vgs) Ids = 88mA 2. Width = 7 um, multiplier = 40 and finger = 1 and Length = .5um @1.5 V(Vgs) Ids =103.6 mA supporting doc link click here @Boris Murmann @Tim Edwards please help me in figure out possible reasons

See this file here. It has the bins of the actual transistors measured to make the transistors models. https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[…]d6f59b57627436/cells/nfet_01v8/sky130_fd_pr__nfet_01v8.bins.csv If you look at the model parameters for each bin, you can look for the differences in VT. Compare the bins 34 (7/0.5 um/um) and 42 (0.42/0.5 um/um). The first one has a 0.497 V the second one has 0.615 V threshold voltage. https://raw.githubusercontent.com/google/skywater-pdk-libs-sky130_fd_pr/f62031a1be9aefe90[…]36/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.pm3.spice The transistor models are greatly simplified, so the drain current is a function only of the aspect ratio W/L, but you should never compare directly their performance, as other properties also changes with it.

thank you so much @Luis Henrique Rodovalho for the reply

@Ashutosh Kumar @Luis Henrique Rodovalho I think the usage of a large no. of bins (with discontinuities at bin boundaries) is an indication of poor device models. I have used the PDKs of several other fabs and they were way better.

Thank you @Hesham Omran for comment. what could be the best practices in this case.

Nothing special, just: • Take sim results with some more skepticism. • Avoid the false impression that all device models are similar to SKY130.