https://open-source-silicon.dev logo
Channels
aa
abcc
activity
adiabatonauts
analog-design
announce
announcements
b2aws
b2aws-tutorial
bag
basebands
beagleboard
bluetooth
board-respin
cadence-genus
cadence-innovus
cadence-spectre
cadence-virtuoso
caravan
caravel
caravel-board
chilechipmakers
chip-yard
chipignite
chipignite2206q_stanford_bringup
chisel
coalition-for-digital-environmental-sustainability
community_denmark_dtu
containers
courses
design-review
design-services
dffram
digital-design
digital-electronics-learners
discord-mods
dynamic-power-estimation
efabless
electric
events
fasoc
fault
foss-asic-tools
fossee-iitb-esim
fossee-iitb-google-sky130
fpga
funding
fuserisc
general
generative-ai-silicon-challenge
genius-vlsi
gf180
gf180mcu
hardware-beginners
help-
ieee-sscs-cac-23
ieee-sscs-dc-21q3
ieee-sscs-dc-22
ieee-sscs-dc-23
ihp-sg13g2
images
infiniband
j-core
japan-region
junk
klayout
latam_vlsi
layouteditor
lvs
lvs-analysis
magic
magical
maker-projects
maker-zone
microwatt
mpw-2-silicon
mpw-one-clean-short
mpw-one-silicon
neuro-mem
nydesign
open_pdks
open-pdk
openadiabaticlogic
openfpga
openhighqualityresonators
openlane
openlane_cloudrunner
openlane-development
openocd
openpositarithmetic
openpower
openram
openroad
opentitan
osu
pa-test-chip
paracells
pd-openlane-and-sky130
picosoc
pll
popy_neel
power
private-shuttle
rad-lab-silicon
radio
rdircd
reram
researchers
rf-mmw-design
rios
riscv
sdram
serdes
shuttle
shuttle-precheck
shuttle-status
silicon-photonics
silicon-validation
silicon-validation-private
sky130
sky130-ci
sky130-pv-workshop
sky65
sky90
skywater
sram
stdcelllib
strive
swerv
system-verilog-learners
tapeout-job
tapeout-pakistan
team-awesome
timing-closure
toysram
travis-ci
uvm-learners
vendor-synopsys
venn
verification-be
verification-fe
verilog-learners
vh2v
vhdl
vhdl-learners
vliw
vlsi_verilog_using_opensource_eda
vlsi_verilog_using_opensoure_eda
vlsi-learners-group
vlsi101
waveform-viewers
xls
xschem
xyce
zettascale
Powered by
Title
a

Ashutosh Kumar

02/10/2023, 4:41 AM
Hi, I have done DC analysis of NMOS setup vdd(Vds) = 1.8v, Vgs vary form 0 to 1.8v 1. Width = 40 um, multiplier = 7 and finger = 1 and Length = .5um @1.5 V(Vgs) Ids = 88mA 2. Width = 7 um, multiplier = 40 and finger = 1 and Length = .5um @1.5 V(Vgs) Ids =103.6 mA supporting doc link click here @Boris Murmann @Tim Edwards please help me in figure out possible reasons
šŸ‘€ 2
l

Luis Henrique Rodovalho

02/10/2023, 9:01 AM
See this file here. It has the bins of the actual transistors measured to make the transistors models. https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[ā€¦]d6f59b57627436/cells/nfet_01v8/sky130_fd_pr__nfet_01v8.bins.csv If you look at the model parameters for each bin, you can look for the differences in VT. Compare the bins 34 (7/0.5 um/um) and 42 (0.42/0.5 um/um). The first one has a 0.497 V the second one has 0.615 V threshold voltage. https://raw.githubusercontent.com/google/skywater-pdk-libs-sky130_fd_pr/f62031a1be9aefe90[ā€¦]36/cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.pm3.spice The transistor models are greatly simplified, so the drain current is a function only of the aspect ratio W/L, but you should never compare directly their performance, as other properties also changes with it.
a

Ashutosh Kumar

02/10/2023, 3:37 PM
thank you so much @Luis Henrique Rodovalho for the reply
h

Hesham Omran

02/12/2023, 2:17 PM
@Ashutosh Kumar @Luis Henrique Rodovalho I think the usage of a large no. of bins (with discontinuities at bin boundaries) is an indication of poor device models. I have used the PDKs of several other fabs and they were way better.
šŸ‘ 1
a

Ashutosh Kumar

02/12/2023, 2:47 PM
Thank you @Hesham Omran for comment. what could be the best practices in this case.
h

Hesham Omran

02/12/2023, 3:23 PM
Nothing special, just: ā€¢ Take sim results with some more skepticism. ā€¢ Avoid the false impression that all device models are similar to SKY130.
šŸ‘ 1