I have a question about the 1.8v nch transistor breakdown voltage, in particular the gate breakdown voltage. I am designing a "bootstrapped gate drive" circuit where the gate is driven above the supply rail. I have searched the skywater docs: https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html#id74 and am only able to find the maximum recommended operating voltages and not the breakdown voltages. Do you know of any documentation that describes the gate breakdown voltage. The following schematic is an example of the circuit that I am using. In the schematic if Vin = VDD, the maximum voltage on the gate with respect ground is 2*VDD. I believe the bootstrapped circuit is ok under quiescent conditions, my concern is the transient condition when the transistor is turning on. If Vout is at 0 volts, Vin is at VDD, and the pass transistor is turning on with the gate going from 0v to 2*VDD, the output drain voltage is momentarily at 0V before it charges up to Vin. Under worse case transient conditions the gate to drain voltage will be 2*VDD.

This circuit is usually built in a way that avoids seeing 2*VDD across the gate oxide. See the classical paper by Abo &Gray.

Do you know the title of the paper?

Thank you.