Hi, @Tim Edwards what I did was to clone this reram repo, then use the

openvaf

compiler (openvaf is a prebuilt executable I downloaded from the openvaf main site). Then simply compiled the

sky130_fd_pr_reram_git/cells/reram_cell/sky130_fd_pr_reram__reram_cell.va

to produce the

sky130_fd_pr_reram__reram_cell.osdi

object. This must be included in ngspice with the new

pre_osd

command. Following is the complete netlist of the testbench:

** sch_path: /home/schippes/.xschem/xschem_library/xschem_sky130/sky130_tests/tb_reram.sch
**.subckt tb_reram
N1 TOP 0 sky130_fd_pr_reram__reram_model
V1 TOP 0 PWL (0 0 1u 2 2u 0 3u -2 4.0u 0.0)
**** begin user architecture code
.control
  * Modify according to your specific location
  pre_osdi /mnt/sda7/sky130_fd_pr_reram_git/cells/reram_cell/sky130_fd_pr_reram__reram_cell.osdi
  save all
  tran 1n 4.0u
  write tb_reram.raw
.endc
** opencircuitdesign pdks install, not needed in this testbench
* .lib /home/schippes/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice tt
**.ends

.model sky130_fd_pr_reram__reram_model sky130_fd_pr_reram__reram_cell area_ox=0.1024e-12  Tox=5.0e-9
+  Tfilament_max=4.9e-9  Tfilament_min=3.3e-9  Tfilament_0=3.5e-9  Eact_generation=1.501  Eact_recombination=1.500
+  I_k1=6.140e-5  Tfilament_ref=4.7249e-9  V_ref=0.430  velocity_k1=150  gamma_k0=16.5  gamma_k1=-1.25
+   Temperature_0=300  C_thermal=3.1825e-16  tau_thermal=0.23e-9  t_step=1.0e-9

**** end user architecture code
.end

You see the reram instance uses the (new)

N

letter, it references a

sky130_fd_pr_reram__reram_model

SPICE model, this can be defined as simply

.model sky130_fd_pr_reram__reram_model sky130_fd_pr_reram__reram_cell

the

.model

'*connects*' the spice device to the verilog OSDI model Additionally the .model can override default parameters specified in the .va file, as done in above netlist . To enable the new reram I think the

.model sky130_fd_pr_reram__reram_model

SPICE wrapper and the

<http://sky130_fd_pr_reram__reram_cell.va|sky130_fd_pr_reram__reram_cell.va>

verilog source file should be added. Then the verilog must be compiled on the target machine in some way.

So

pre_osdi

has to be run in a control block? Is there a way to run it like a dot-card so that it would get enabled by calling

.lib

?

@Tim Edwards I don't know much about that, but it seems

pre_osdi

needs to be at the beginning of a

.control

, see the attached manual page. I have verified that having this:

.control
  pre_osdi <.....osdi model>
.endc

.save all
.tran 1n 2u
...

works calling ngspice in batch mode, or this one works in interactive mode:

.control
pre_osdi <.....osdi model>
.endc

.control
  save all
  tran 1n 2u
  write tb_reram.raw
.endc